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WB1315
Dual Serial Input PLL with 2.5-GHz Prescalers
Features
* Operating voltage 2.7V to 5.5V * PLL1 and PLL2 operating frequency: -- 2.5 GHz with prescaler ratios of 32/33 or 64/65 * Lock detect feature * Power-down mode ICC < 1 A typical at 3.0V * 20-pin TSSOP (Thin Shrink Small Outline Package)
Applications
The Cypress WB1315 is a dual serial input PLL frequency synthesizer designed to combine the Transmit and Receive RF frequency sections of wireless communications systems. Two 2.5-GHz prescalers, each with pulse swallow capability are included. The device operates from 2.7V and dissipates only 38 mW.
WB1315 Dual Hi-Lo PLL Block Diagram
GND (4) GND (7) VCC1 (1) VCC2 (20) VP1 (2)
FIN1 (5) FIN1# (6)
Prescaler 32/33 or 64/65
Binary 7-Bit Swallow Counter
Binary 11-Bit Programmable Counter
fp1 Phase Detector Charge Pump
DOPLL1 (3)
19-Bit Latch OSC_IN (8)
Pwr-dwn PLL1 fr1 fr fp Monitor Output Selector
15-Bit Reference Counter Latch Selector LE (13) DATA (12) CLOCK (11) 20-Bit Latch 20-Bit Latch 15-Bit Reference Counter 19-Bit Latch Pwr-dwn PLL2
FO /LD (10)
fr2
Cntrl 22-Bit Shift Reg.
Power Control
FIN2 (16) FIN2# (15)
Prescaler 32/33 or 64/65
Binary 7-Bit Swallow Counter
Binary 11-Bit Programmable Counter
Phase Detector fp2
Charge Pump
DOPLL2 (18)
GND (14)
GND (9)
GND (17)
VP2 (19)
Pin Configuration
VCC 1 VP1 DOPLL1 GND FIN 1 FIN1# GND OSC_IN GND FO/LD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC2 VP2 DOPLL2 GND FIN 2 FIN 2# GND LE DATA CLOCK
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 February 2, 2000, rev. *A
WB1315
VP1
10 F
VCC 2.7-5.5V
10 F 10 F
VP2
0.1 F 0.1 F 100 pF 0.1 F
(1) VCC1
100 pF
(20) VCC2
100 pF 0.1 F
0.1 F
(2) VP1
100 pF
(19) VP2
100 pF 0.1 F
100 pF
2.5 GHz VCO
22 k 3.3 k 68 pF 0.01 F
(3) DOPLL1 DOPLL2
(18)
3.3 K
22 k
2.5 GHz VCO
0.001 F (4)
(17) 0.001 F GND GND
0.1 F
68 pF
18
18
1000 pF
(5) FIN 1 FIN2
(16) 1000 pF
18
18
18
51
51
18
(6) RF LO
100 pF
(15) FIN 1# FIN2#
100 pF
IF LO
(7) GND GND
(14)
1000 pF
(8) OSC_IN LE
(13)
2 k
51
3 k
(9) GND DATA
(12)
2 k
3 k
(10) FO/LD CLOCK
(11)
2 k
3 k
Figure 1. Application Diagram Example - WB1315 2.5-GHz Dual Hi/Hi PLL
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WB1315
Pin Definitions
Pin Name VCC VP1 DOPLL1 GND FIN1 FIN1# GND OSC_IN GND FO/LD Pin No. 1 2 3 4 5 6 7 8 9 10 Pin Type P P O G I I G I G O Pin Description Power Supply Connection for PLL1 and PLL2: When power is removed from both the VCC1 and VCC2 pins, all latched data is lost. PLL1 Charge Pump Rail Voltage: This voltage accommodates VCO circuits with tuning voltages higher than the V CC of PLL1. PLL1 Charge Pump Output: The phase detector gain is IP/2. Sense polarity can be reversed by setting the FC bit in software (via the Shift Register). Analog and Digital Ground Connection: This pin must be grounded. Input to PLL1 Prescaler: Maximum frequency 2.5 GHz. Complementary Input to PLL1 Prescaler: A bypass capacitor should be placed as close as possible to this pin and must be connected directly to the ground plane. Analog and Digital Ground Connection: This pin must be grounded. Oscillator Input: This input has a VCC/2 threshold and CMOS logic level sensitivity. Reference Ground Connection: This pin must be grounded. Lock Detect Pin of PLL1 Section: This output is HIGH when the loop is locked. It is multiplexed to the output of the programmable counters or reference dividers in the test program mode. (Refer to Table 3 for configuration.) Data Clock Input: One bit of data is loaded into the Shift Register on the rising edge of this signal. Serial Data Input Load Enable: On the rising edge of this signal, the data stored in the Shift Register is latched into the reference counter and configuration controls, PLL1 or PLL2 depending on the state of the control bits. Analog and Digital Ground Connection: This pin must be grounded. Complementary Input to PLL2 Prescaler: A bypass capacitor should be placed as close as possible to this pin and must be connected directly to the ground plane. Input to PLL2 Prescaler: Maximum frequency 2.5 GHz. Analog and Digital Ground Connections: This pin must be grounded. PLL2 Charge Pump Output: The phase detector gain is IP/2. Sense polarity can be reversed by setting the FC bit in software (via the Shift Register). PLL2 Charge Pump Rail Voltage: This voltage accommodates VCO circuits with tuning voltages higher than the V CC of PLL2. Power Supply Connections for PLL1 and PLL2: When power is removed from both the VCC1 and VCC2 pins, all latched data is lost.
CLOCK DATA LE
11 12 13
I I I
GND FIN2# FIN2 GND DOPLL2 VP2 VCC2
14 15 16 17 18 19 20
G I I G O P P
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WB1315
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating Parameter VCC or VP VOUT IOUT TL TSTG Output Voltage Output Current Lead Temperature Storage Temperature Description Power Supply Voltage only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +6.5 -0.5 to V CC+0.5 15 +260 -55 to +150 Unit V V mA C C
Handling Precautions
Devices should be transported and stored in antistatic containers. These devices are static sensitive. Ensure that equipment and personnel contacting the devices are properly grounded. Cover workbenches with grounded conductive mats.
Always turn off power before adding or removing devices from system. Protect leads with a conductive sheet when handling or transporting PC boards with devices. If devices are removed from the moisture protective bags for more than 36 hours, they should be baked at 85C in a moisture free environment for 24 hours prior to assembly in less than 24 hours.
Recommended Operating Conditions
Parameter VCC1, VCC2 VP TA Description Power Supply Voltage Charge Pump Voltage Operating Temperature Ambient air at 0 CFM flow Test Condition Rating 2.7 to 5.5 VCC to +5.5 -40 to +85 Unit V V C
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WB1315
Electrical Characteristics: VCC = VP = 2.7V to 5.5V, TA = -40C to +85C, Unless otherwise specified
Parameter ICC IPD FIN1, FIN2 FOSC F PFIN1, PFIN2 PFIN1, PFIN2 VOSC IIH, IIL VIH VIL IIH IIL VOH VOL IDOH(SO) IDOL(SO) IDOH(SI) IDOL(SI) IDO Oscillator Input Sensitivity Oscillator Input Current High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High level Output Voltage Low Level Output Voltage IDO High, Source Current IDO Low, Source Current IDO High, Sink Current IDO Low, Sink Current IDO Charge Pump Sink and Source Mismatch VCC = V P = 3.0V, DO = VP/2 [IIDO(SI)I - IIDO(SO)I]/ [1/2*{IIDO(SI)]I+IIDO(SO)I}]*100% -40CIDO vs T IOFF
Charge Pump Current Variation vs Temperature High Impedance Leakage Current
5 2.5
% nA
Notes: 1. 2.0 GHz < FIN < 2.5 GHz. 2. FIN < 2.0 GHz. 3. IDOvs T; Charge pump current variation vs. temperature. [IIDO(SI)@T I - IIDO(SI)@25 CI]/IID O(SI)@25CI * 100% and [IIDO(SO)@TI - IIDO(SO)@25CI]/IID O(SO)@25CI *100%.
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WB1315
Timing Waveforms
Key:
FC Bit HIGH FC Bit LOW (Refer to Table 2 for meaning of FC bit.) Increasing Frequency VCO Characteristics Phase Comparator Sense
Increasing Voltage
Phase Detector Output Waveform
FR
FP tw tw
LD
DO Charge Pump Output Current Waveform
FR
FP tw tw
Do
IDO
Three-state
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WB1315
Timing Waveforms (continued)
Serial Data Input Timing Waveform[4, 5, 6, 7]
// DATA PD = MSB PRE // B1 A7
// CNT2 // CNT1 = LSB
CLOCK // t1 LE // // t2 // t3 t5 t4
Serial Data Input
Data is input serially using the DATA, CLOCK, and LE pins. Two control bits direct data into the locations given in Table 1. Table 1. Control Configuration CNT1 0 0 1 1 CNT2 0 1 0 1 Function Program Reference 2: R = 3 to 32767, set PLL2 (low frequency) phase detector polarity, set current in PLL2, set PLL2 three-state, set monitor selector to PLL2. Program Reference 1: R = 3 to 32767, set PLL1 (high frequency) phase detector polarity, set current in PLL1, set PLL1 three-state, set monitor selector to PLL1 Program Counter for PLL2: A = 0 to 63, B = 3 to 2047, set PLL2 prescaler ratio, set power-down to PLL2. Program Counter for PLL1: A = 0 to 63, B = 3 to 2047, set PLL1 prescaler ratio, set power-down to PLL1.
Notes: 4. t1-t5 = 50 s > t > 0.5 s. 5. CLOCK may remain HIGH after latching in data. 6. DATA is shifted in with the MSB first. 7. For DATA definitions, refer to Table 2.
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WB1315
Table 2. Shift Register Configuration[8] 1 2 3 4 R2 5 R3 6 R4 7 R5 8 R6 9 R7 10 R8 11 R9 12 13 14 15 16 17 18 19 IDO 20 TS 21 LD 22 FO Reference Counter and Configuration Bits CNT1CNT2 R1 R10 R11 R12 R13 R14 R15 FC
Programmable Counter bits CNT1CNT2 A1 Bit(s) Name CNT1, CNT2 R1-R15 FC IDO TS LD FO PRE PD A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 PRE PD
Function Control Bits: Directs programming data to PLL1 or PLL2. Reference Counter Setting Bits: 15 bits, R = 3 to 32767.[9] Phase Sense of the Phase Detector: Set to match the VCO polarity, H = + (Positive VCO transfer function). Charge Pump Setting Bit: IDO HIGH = 3.8 mA, IDO LOW = 1 mA. Three-state Bit: Three-states the DO output for PLL2 and PLL1 when HIGH. Lock Detect: Directs the lock detect signal source pin 10. Pin 10 is HIGH with narrow low excursions when locked. When not locked, this pin is LOW. Frequency Out: This bit can be set to read out reference or programmable divider at the LD pin for test purposes. Prescaler Divide Bit: For PLL1 and PLL2: LOW = 32/33 and HIGH = 64/65. Power-down: LOW = power-up and HIGH = power-down. FIN is at a high-impedance state, respective B counter is disabled, forces three-state at DO outputs and phase comparators are disabled. The reference counter is disabled and the OSC input is high-impedance after both PLLs are powered down. Data can be input and latched in the power-down state. Swallow Counter Divide Ratio: A = 0 to 63 for both PLL1 and PLL2. Programmable Counter Divide Ratio: B = 3 to 2047.[9]
A1-A7 B1-B11
Table 3. FO/LD Pin Truth Table FO (Bit 22) PLL1 0 0 0 0 0 1 0 1 1 1 1 PLL2 0 0 0 0 1 0 1 0 1 1 1 PLL1 0 0 1 1 X X X X 0 1 1
LD (Bit 21) PLL2 0 1 0 1 0 0 1 1 1 0 1 Disable PLL2 Lock Detect PLL1 Lock Detect PLL1/PLL2 Lock Detect PLL2 Reference Divider Output PLL1 Reference Divider Output PLL2 Programmable Divider Output PLL1 Programmable Divider Output PLL2 Counter Reset PLL1 Counter Reset PLL1/PLL2 Counter Reset FO/LD Pin Output State
Notes: 8. The MSB is loaded in first. 9. Low count ratios may violate frequency limits of the phase detector.
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WB1315
Table 4. 7-Bit Swallow Counter (A) Truth Table[10] Divide Ratio A PLL1 0 1 ::: 62 63 PLL2 0 1 ::: 62 63 X X ::: X X 0 0 ::: 1 1 0 0 ::: 1 1 0 0 ::: 1 1 0 0 ::: 1 1 0 0 ::: 1 1 0 1 ::: 0 1 X X ::: X X 0 0 ::: 1 1 0 0 ::: 1 1 0 0 ::: 1 1 0 0 ::: 1 1 0 0 ::: 1 1 0 1 ::: 0 1 A7 A6 A5 A4 A3 A2 A1
Table 5. 11-Bit Programmable Counter (B) Truth Table[11] Divide Ratio B 3 4 ::: 2046 2047 B11 0 0 ::: 1 1 B10 0 0 ::: 1 1 B9 0 0 ::: 1 1 B8 0 0 ::: 1 1 B7 0 0 ::: 1 1 B6 0 0 ::: 1 1 B5 0 0 ::: 1 1 B4 0 0 ::: 1 1 B3 0 1 ::: 1 1 B2 1 0 ::: 1 1 B1 1 0 ::: 0 1
Table 6. 15-Bit Programmable Reference Counter (for PLL1 and PLL2) Truth Table[11] Divide Ratio R 3 4 ::: 32766 32767 R15 0 0 ::: 1 1 R14 0 0 ::: 1 1 R13 0 0 ::: 1 1 R12 0 0 ::: 1 1 R11 0 0 ::: 1 1 R10 0 0 ::: 1 1 R9 0 0 ::: 1 1 R8 0 0 ::: 1 1 R7 0 0 ::: 1 1 R6 0 0 ::: 1 1 R5 0 0 ::: 1 1 R4 0 0 ::: 1 1 R3 0 1 ::: 1 1 R2 1 0 ::: 1 1 R1 1 0 ::: 0 1
Ordering Information[12]
Ordering Code WB1315 Package Name X Package Type 20-pin TSSOP (0.173" wide) TR Tape and Reel Option
Notes: 10. B is greater than or equal to A. 11. Divide ratio less than 3 is prohibited. The divide ratio can be calculated using the following equation: fvco = {(P * B) + A} * fosc / R where (A < B) fvco: Output frequency of the external VCO. fosc: The crystal reference oscillator frequency. A: Preset divide ratio of the 7-bit swallow counter (0 to 127). B: Preset ratio of the 11-bit programmable counter (3 to 2047). P: Preset divide ratio of the dual modulus prescaler (64/65 or 128/129). R: Preset ratio of the 14-bit programmable reference counter (3 to 16383). The divide ratio N = (P * B) + A. 12. Operating temperature range: -40C to +85C.
Document #: 38-00825-A
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WB1315
Package Diagram
20-Pin Thin Shrink Small Outline Package (TSSOP, 0.173" wide)
Physical Dimensions In Millimeters 20 Lead (0.173" Wide) TSSOP Package Order Number X 20" clear antistatic tubes, 76 units/tube JEDEC Outline MO-153
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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